1. Field of the Invention
The invention relates to a non-volatile semiconductor memory device, and more particularly to a reading method of a NAND-type flash memory.
2. Description of the Related Art
A conventional NAND-type flash memory comprises a memory array consisting of a plurality of NAND strings arranged in a matrix form. The NAND string comprises a plurality of memory cells connected in serial, a bit line select transistor connected to one end of the NAND string and a source line select transistor connected to the other end of the NAND string. FIG. 1 is a circuit diagram illustrating a structure of NAND strings. In the memory array, a plurality of NAND strings (referred to as cell units NU thereinafter), each of which comprises a plurality of memory cells connected in serial, is formed in a matrix form. In the example as shown in FIG. 1, a cell unit NU is composed of 32 memory cells MCi (i-0, 1, . . . , 31) connected in serial, a bit line select transistor BST connected to one end of the cell unit NU and a source line select transistor SST connected to the other end of the cell unit NU. The drain of the bit line select transistor BST is connected to a corresponding bit line GBL, and the source of the source line select transistor SST is connected to a common source line SL. The control gate of the memory cell MCi is connected to a word line WLi. The gate of the bit line select transistor BST and the gate of the source line select transistor SST are respectively connected to select gate lines SGD and SGS, which are extended in parallel with the word lines WLi.
Generally speaking, each memory cell includes source/drain of N-type diffusion region, a tunnel oxide film formed on a channel between the source and the drain, a floating gate (charge accumulation layer) formed on the tunnel oxide film, and a control gate formed on the floating gate through a dielectric layer. Conventionally, when no charge is accumulated in the floating gate, that is, when data “1” is written, the threshold is negative and the memory cell is normally on. When electrons are accumulated in the floating gate, that is, when data “0” is written, the threshold is shifted toward a positive value and the memory cell is normally off.
In a reading operation, a low-level voltage (L level, for example, 0 V) is supplied to the control gate of the selected memory cell and a high-level voltage (H level, for example, 4.5 V) is supplied to the control gates of those unselected memory cells, so as to turn on the bit line select transistor BST and the source line select transistor SST and detect the voltage level of the bit line GBL. In a programming writing-in) operation, a voltage of 0 V is supplied to the P-well of the substrate, the drain, the channel, and the source of the memory cell, a H level programming voltage Vpgm (for example, 20 V) is supplied to the control gate of the selected memory cell, an intermediate-level voltage (for example, 10 V) is supplied to the control gates of those unselected memory cells, so as to turn on the bit line select transistor BST and turn off the source line select transistor SST, and a voltage level corresponding to data “0” or “1” is supplied to the bit line GBL. In an erasing operation, a voltage of 0 V is supplied to the control gates of the selected memory cells in a memory block, a H level voltage (for example, 20 V) is supplied to the P-well, and electrons in the floating gates are pulled to the substrate, so as to erase data in unit of block.
In a NAND flash memory, a page buffer is used to read data from or write data into the memory array. When reading data, data in a selected page of the memory array is transmitted in parallel to the page buffer via the bit lines, and data stored in the page buffer is output in serial according to a clock signal. When writing data, data is input into the page buffer in serial according to a clock signal, and then the data is written from the page buffer into the selected pages of the memory array via the bit lines. In a NAND flash memory as disclosed in the patent document 1, address information is input and a page is selected according to the address information. When data in the selected page is transmitted from the memory array to the page buffer, the NAND flash memory outputs a busy signal indicating that external access is prohibited. After the data transmission is completed, the NAND flash memory outputs a ready signal indicating that external access is allowed.